2015/8/27 上午 10:21:40        Administrator        General   0 Comments
Pros and Cons of single-ended signal transmissions
Pros: Simpler signal management, lower wiring costs
Cons: Higher working voltage, more prone to interference for higher frequencies
Currently, signal-ended signals, which are still being used by interface like that of PCI Buses, ISA Buses, LPC buses, etc, referenced the clock as its timing, making it a key factor in influencing the stability of the signal’s transmission/ reception.
During an experience sharing session on a customized motherboard of a European client, AAEON discovered that when the single end waveforms (33 MHz and 14.318 MHz) on an AMD FT1 platform are measured, their rise edge rate and fall edge rate will not match what is specified in the specification. See the tables below. 

For the purpose upholding the internal design quality of AAEON, and improving the boar’s stability, it is highlighted in the systems of ESS experts: Functional testing may be normal, but the board should still attain the quality standards of SI signals when measured. Following the technical documents provided by AMD, it should be noted that a 50pF load capacitor is required for both the rising and falling slew rate, as highlighted in red in the table below.

A 47 pF capacitor is subsequently added at the single clock end.
Please note that measuring from different positions may lead to varying results. The results of re-measured SI signals (with the point the measurement is taken and the measured data) are as shown:

The reference waveform for SI verification
The measured waveform from the PCH

The measured waveform from the PC104 connector

Note: As the length of the layout is different from the component connected at the single clock end, it is through varying the capacitance of the load capacitor needed based on the actual situation that we can deliver a product with both quality and stability to our customers. 
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