SMARC Design


  2015/8/12 下午 06:47:07        Administrator        General   2 Comments
                                
SMARC (Smart Mobility ARChitecture) is a new embedded module design created for the low power consuming, low cost, and high performance market. With ARM-based SoCs as well as other low power consuming platforms serving as the core of the design, the power consumption of the entire module should not exceed 6W, an amount that significantly differs from its COM Express counterparts which are based on the x86 PC architecture and may have a designed power rating of more than 100 W. Also, unlike conventional PC interface such as USBs, PCI, PCIe, PCIe Graphics, and LPCs supported by COM Express platforms, SMARC interface are much more oriented towards common ARM interface like the I2S bus, USB client/ host modes (OTG), SD, eMMC, MIPI CSI,etc.
 
SMARC can be divided into two sizes: 82 x 50 mm and 82 x 80 mm. And uses 314-pin MXM connectors for board-to-module communications. See Table 1 for the main differences between COM Express and SMARC.
 
Item COM Express SMARC
Main Design Platform x86 PC architecture ARM architecture
Designed Power Rating More than 100W Less than 6W(ARM-Based Designs)
Common Interface Conventional PC Interface:
USB, PCI Express, PCI Express Graphics, LPC, PCI…
Common ARM Interface
I2S, USB client/host mode(OTG), SD and eMMC, CSI…
Dimensions 110 × 155 mm (4.3 × 6.1”) (extended)
95 × 125 mm (3.7 × 4.9”) (basic)
95 × 95 mm (3.7 × 3.7”) (compact)
55 × 84 mm (2.2 × 3.3”) (mini)
82 x 50 mm
82 x 80 mm
Board-to-module Interface Board-to-board connectors 314 pin MXM Connector
 
Intel®’s Atom™ E3800 Series CPUs are chosen for powering AAEON’s latest SMARC module, the μCOM-BT. And the reason behind this decision lies in the chip’s 22 nm manufacturing process that adequately makes the chip’s power consumption comparable to that of ARM-based platforms. This series of Atom processors also performed exceptionally better in terms of computing, graphic processing, and media playing capabilities than its older iterations. However, as the E3800 series are, after all, x86 platforms, this article will be exploring the process of designing them to the SMARC specifications.

There are four main aspects in the design process
  1. Power
  2. I/O Voltage Level
  3. Differences between x86 and ARM interface
  4. Charger Control
AAEON’s μCOM-BT has a form factor of 82 x 50 mm, the smallest of the SMARC form factor. Since the small dimension may not offer enough room if it follows the traditional x86 discrete power design layout, the PMIC (Power Management IC) by ROHM are adopted for dedicated power management. Though this solution, not only lesser room is needed for components, all the power sequence timing control are included without the need for extra sequence control.

Next we will be looking into I/O voltage levels, which are defined at +3.3 V or 1.8 V for the SMARC specification. Intel’s traditional x86 platform usually uses 3.3V for logic control, but the unique E3800 series instead uses 1.8V. The μCOM-BT, after much consideration, opts for 1.8 V as its designed voltage level, necessitating conversion for other non-1.8V signals. The main area of concern is using different level shifter for different signals, such as high-speed, low-speed, open-drain, and push-pull signals, as appropriate level shifters are required so as to avoid abnormality after the conversion.

The third aspect to be discussed is the differences in interface defined by the SMARC specification and the traditional x86 PC architecture. For instance, the abovementioned I2S, USB client/ host mode (OTG), SD, eMMC, etc are examples not found in the x86 architecture. Since the E3800 Series is aimed at the low power consuming ARM market, these features are specially incorporated into the chips. But the issue of software support for these features should be noted, as only drivers listed explicitly by Intel for specific operating systems are supported. 

Lastly, the charging/ discharging of the battery will be explored. With “M” being “Mobility” in SMARC, batteries naturally falls within the SMARC specification. In terms of hardware designs, mechanisms relating to the charging and discharging of the battery must be in place. For the μCOM-BT, this is accomplished in form of using EC as a controller for the battery’s charging/ discharging, with special attention taken to ensure the EC voltage level matches the defined level.

In conclusion, the result of incorporating the powerful Intel® Atom™ E3800 Series CPUs into the low power consuming SMARC modules is a combination that holds extremely high competitive advantage. Furthermore, such setups can be used with a flexible range of operating systems that include the common Windows Embedded to other open source OS. We believe more low power consuming x86 platforms of such nature will be launched in the future, popularizing the use of x86 platforms on the SMARC form factor. With that, AAEON will always stay at the forefront of the industry.
 
2 Comments
  • Commented on 2016/1/21 下午 07:26:42

    AAEON whether there is support for power charging function of Carrier Board design products for SMARC ?

  • Commented on 2016/1/21 下午 08:11:38

    Yes, AAEON's board ECB-960 model has to support this feature and verify that this function is good. Suggestions can refer catalog for more product information.

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