SATA 3.0

Verification and Correction of Intel PhyTune SATA Tool Signals

  2015/4/8 下午 03:52:30      Ron Liao      General   0 Comments

For designers of industrial computers, tailoring systems to different requirements is a task that is almost irsurmountable. As the application of the board may lead to different design changes, it is common that such changes cause problems to arise. Thus, the key factors for development teams to win this fiercely contested market are their abilities to tackle these problems and boosting the quality of their signals. With years of experience and professional knowledge, members of AAEON’s R&D team are all extremely proficient troubleshooters, and the following is their experience in using PhyTune SATA Tool in correcting the Intel® 8 Series Chipset.
From SATA1.0 (1.5Gb/s) to SATA3.0 (6.0Gb/s), SATA (Serial ATA) applications have seen a great leap in transfer speed. Through the use of the SATA Eye Diagrams as well as high precision measuring tools, AAEON’s hardware development team managed to get a better picture in whether the quality of high-speed signals still met any stipulated standards during the transmission process, regardless of SATA-GEN1 or SATA-GEN3. For the Intel® 8 Series Chipset, the PhyTune SATA Tool can be used to compare and adjust SATA Eye Diagrams in real time. Image 1 shows the statuses of the related parameters for SATA port 0. Among the more important adjustable parameters are the output voltage swing; which simultaneously affects the strength of the output voltage waves when modified, restoring original signals with De-emphasis and the Register Values for BIOS; which simultaneously change any register values stored there when any parameters are modified. For modifications using the abovementioned tools, a set of SATA port is selected while measuring for the quality of high-speed signals and a set of optimized registered values for BIOS and a set of address will be shown.
Image 1.SATA Port Information and PhyTune Tool Interface   

                          Image 2. Intel Chipset Specifications
The registered value is then written into the SATA address of corresponding chipset in the BIOS. As shown in Image 2, the SATA definition index is highlighted in the chipset specification. Each time the system is power on, the registered value in the BIOS will be read and the adjusted SATA eye diagram will be outputted, ensuring the strength of the high-speed signals during transmission. Different cad designs, such as cable length and PCB stack structures will directly affect the parameters of their respective PhyTune Tools, and excessive adjustments or performing adjustments with a lack of knowledge on the definitions of various parameters will also have an adverse effect on the system. Image 3 and 4 respectively showed the eye diagrams before and after PhyTune Tool adjustments. From these images it is revealed that when adjustments of the PhyTune Tool is applied on SATA CONN and boards of the same model, its SATA signals are appropriately corrected, thereby achieving the best output in both the testing phase as well as actual SATA applications.
Image 3. Initial Eye Diagram Measurement Prior PhyTune Adjustment          

 Image 4. Initial Eye Diagram Measurement After PhyTune Adjustment

The PhyTune SATA Tool not only replaces the traditional method of measuring resistance, it also shortens the troubleshooting time during development, saving the trouble of repeating the correction and debugging of the board’s SATA features and fulfilling the cilent’s needs. In order for this verification method to work, proficiency and strict quality standards are needed, and the Intel PhyTune SATA has once again proved the professionalism of AAEON’s development team as well as the stability of their products.

Mini PCIe/mSATA Sharing

  2015/5/11 下午 03:20:51      Administrator      General   0 Comments
PCI, CFD, Cfast, Mini-Card are just some of the many communication and storage interfaces found in a modern day PC system. Subjected to different limitations and applications, each connector provided cilents options to integrate different devices to fulfill their needs. In particular, the Mini-Card connectors, initially used for Mini-PCIe modules, can be used for other types of hardware as well, in this case, the Mini-SATA (mSATA) storage devices.   
mSATA/PCIE; or Mini-PCIe socket (PCIe +USB), compatible with mSATA
This function has already been incorporated in many of AAEON’s products, it can be found described as:
mSATA/PCIE; or Mini-PCIe socket (PCIe +USB), compatible with mSATA
Early products go through BOM to achieve the purpose of supporting Mini-PCIe or mSATA. These products, when first assembled, supports only Mini-PCIe signals. Should the cilent specifically asks for mSATA compatibility, it can be done upon the completion of the machine’s assembly. However, reversing back to the former state can only be accomplished via the reworking of parts at a factory level. Though this method permits compatbility for both interfaces, it is done at the expense of flexibility at the cilent’s end.
With considerations being put to convenience and usability, a much more strip-down has been created for providing support to both types of signals. By performing the required configuration directly to the system’s BIOS (basic input/output), users simply needs to select their desired settings and connect the supported devices (mini-PCIe or mDATA) to begin using them immediately.
To implement this function, ICs and routing specific to high-speed signal conversion are adopted and created. Comparing the pin definitions of both Mini-PCIe and mSATA on a Mini-Card connector, two main differences are noted:

1. Designed input voltage
Mini-PCIe require +3.3Vaux of power to start up, meaning it is still drawing power even during hibernation (see p24 of table-1). This is due to the “awake” mechanism of Mini-PCIe.
mSATA require +3.3V to start up, and power can be cut-off during hibernation. As the result this source voltage of 3.3V must also be converted as the BIOS selects Mini-PCIe or mSATA.
Pin # mSATA Description Mini-PCIe
P23 +B Host Receiver Differential Signal Pair PERn0
P24 +3.3V 3.3V Source +3.3Vaux
P25 -B Host Receiver Differential Signal Pair PERp0
P26 GND Return Current Path GND
P27 GND Return Current Path GND
P28 1.5V 1.5V Source 1.5V
P29 GND Return Current Path GND
P30 Two Wire Interface Two Wire Interface Clock3 SMB_CLK
P31 -A Host Transmitter Differential Signal Pair PETn0
P32 Two Wire Interface Two Wire Interface Data3 SMB_DATA
P33 +A Host Transmitter Differential Signal Pair PETp0
P34 GND Return Current Path GND
P35 GND Return Current Path GND
P36 Reserved No Connect USB_D-
P37 GND Return Current Path GND
P38 Reserved No Connect USB_D+
P39 +3.3V 3.3V Source +3.3Vaux
P40 GND Return Current Path GND
P41 +3.3V 3.3V Source +3.3Vaux
P42 Reserved No Connect LED_WWAN#
P43 GND Return Current Path GND
P44 Reserved No Connect LED_WLAN#
                    Table-1 mSATA vs Mini-PCIe pin definition table
2. High-speed Signals Conversion
The conversions of Mini-PCIe and mSATA signals are done mainly in pin23, 25, 31, 33. For this the CTBL2042A of NXP is used. As shown in Figure 1, signals from the main chipset (PCIe-mSATA) go through CTBL02042A and are transferred to the Mini-Card connectors.

                Figure-1 Mini-Card/mSATA sub-system block diagram

As shown in figure 2, signal management on the PCB will be optimised based on the recommendations of CTBL02042A

Tests will also be conducted on signals on the Mini-Card connectors, for instance, compatibility tests and eye diagram tests on PCIe and SATA signals. This is done not only to ensure that signals are within standards, but also to boost the compatibility of supported devices.
In addition to providing assurance to the general function of Mini-Card, the abovementioned designs may also offer clients much more flexibility while using these two interfaces.