Schmitt Trigger in Noise Suppression

  2016/2/1 下午 12:03:36      Administrator      General   0 Comments
Schmitt Trigger in Noise Suppression

Noises are typically found in digital circuits. And they frequently cause errors in their applications, affecting the accuracy of the applicable data. This article will be elaborating more on how Schmitt Triggers can be used to suppress these noises.

In common logic gates, when the input signal is greater than Vih, the output will be treated as 1; when it is smaller than Vil, the output will be treated as 0;
As the strength (voltage) between Vih and Vil may also be treated as 1s or 0s, it is generally not recommended to operate at this range of voltages. In addition, the rise time, fall time, and glitch that exist in an actual signal may also be treated as 1s and 0s. Please refer to the graph below.

In observation of the above mentioned discrepancy, a Schmitt trigger can be applied in suppressing this noise, as the output will be treated as one only when the input signal is VT+ (Positive-going input threshold voltage); zero when it is smaller than VT- (Negative-going input threshold voltage). Though the range between VT+ and VT- can be vague, it can additionally be used as a noise suppression zone as shown in the graph below.

Schmitt triggers are best applied in applications with the Vcc range of 1.65 – 5.5 V, albeit careful attention is needed when applying the operating voltage. If the signal is at 3.3 V, the same voltage should be used. If 5 V is used, the signal will never attain VT+, rendering the output permanently as 0. 

The above mentioned method of noise suppression with Schmitt triggers has already seen usage in many applications. However, true signal accuracy can only be achieved in a real life scenario if the properties of the signal are known and the appropriate solution applied.


RTC time delay at computing system

  2016/1/30 上午 11:06:41      Administrator      General   0 Comments

    Making up a computer system is various electronic components; from as critical as the CPU and North and South Bridge, to smaller peripherals/ICs and other passive components, each and every part has to undergo testing based on their application. This article in particular will be shedding more light to the application of the real-time clock (RTC) and its associating measurements.
    The RTC is a piece of electronic equipment that outputs the actual time. As it normally appeared in form of an IC, it is also referred to as the clock chip, a name most commonly used in PCs, embedded systems or handheld devices.
    While some of the RTCs get its pulse from a quartz crystal unit, some of them use the frequency of its AC power source. In case of the former, the frequencies of the unit will be the same that of the quartz crystal at 32.768 kHz, which is equivalent to 215 per second and can be easily implemented with a binary calculator. Among these applications, many replied on an accurate yet stable oscillating frequency, making analyzing the loop for quartz crystal units circuits all the more important. If the circuit can be checked and tested during the design phase, the best circuit combination and system stability can be achieved.
  Points to take note of in circuit analyses
  The three basic elements in analyzing oscillating circuit loops are as follows:
1. Measuring Frequency Tolerance
    The frequency tolerance is defined as the difference between the frequency of a resonating quartz crystal on an oscillating PCB and the center frequency. The formula is as follows:

Frequency tolerance = (Measured frequency – Center frequency) / Center frequency x 1,000,000 (the answer to be in ppm)

Eg: If the center frequency is 32.76800 kHz and measured frequency at 32.76824 kHz, the frequency tolerance will be roughly +7.32 ppm.
    Different electronic products have different frequency tolerance. In the case of quartz crystals, a tolerance of a second per day will amount to roughly ±11.57 ppm and the acceptable range for RTCs is around 0 ppm to 10 ppm, with variations depending on functions. As there is a possibility of system instability, including irregular RTC timing, data error stemming from unsynchronized system frequencies, and noisy or flickering pictures, if the actual output frequency exceeds the permitted the frequency tolerance, frequency tolerance measurements in an oscillating circuit should not be causally overlooked.
2. Driver Level (DL) Measurements
                Driver level can be referred to as the power consumption (in μW) of a quartz crystal unit and can be obtained through multiplying the current measured when it passes through the crystal with its own equivalent impedance. This number has to be smaller than the maximum value as defined on the specification of each crystal. It can be calculated with the following formula.
P (uW) = I2 xRe and Re=R1(1+C0/CL)2
    The design of an oscillating circuit must guarantee a suitable power level so that the oscillation of the quartz crystal unit can be sustained. And typically a smaller figure is preferred. Besides saving energy, it is also a matter of stability of the circuit and the longevity of the quartz crystal; if the power level is too high, the nonlinearity of the crystal will be upset and the quality of the interface for the crystal, electrode, and other materials will be deteriorated, leading to extreme variations to the oscillating frequency and equivalent impedance.
    Operations under overly high power levels may cause the quartz to become unstable. Quoting a 32 kHz crystal, such exposures may cause cracking in the crystal’s internal tuning fork structures; to MHz-grade AT crystals, frequency hopping may occur, affecting its longevity and reliability.
3. Negative Resistance (aka Frequency Deviation) Measurements
    Negative resistance represents the severity of frequency deviation in an oscillating circuit, which, in other words, the health of the circuit, determined by the ease of which the crystal is to oscillate when driven. Negative resistance is a value nonexistent in real life, it is achieve through placing an additional resistor besides a quartz crystal to simulate if the whole oscillating circuit oscillates normally when the crystal’s internal ESR increases.
    The greater the negative resistance denotes the easier an oscillating circuit is to oscillate; when value is too small, it means that the circuit is too slow in making oscillations, or even not oscillating at all. The basic negative resistance of a quartz crystal is estimated to be 3-5 times greater than the maximum ESR value of the crystal.
Case study:
Measuring and Matching Circuits for Quartz Crystal Units.
ETC standard : Frequency deviation / DL / -R
IC: Intel / CG82NM10

    During testing, the capacitance and resistance will be adjusted to obtain the abovementioned (DL/ -R) and the RTC will be optimized for implementation.
    This method is helpful in increasing the accuracy of the RTC and ensures normal operation. In addition to designing general functionality, AAEON’s design team took careful attention to other fine details, such as fine-tuning and debugging its products, so as to satisfy the needs of its customers.

Single end waveform measurement

  2015/8/27 上午 10:21:40      Administrator      General   0 Comments
Pros and Cons of single-ended signal transmissions
Pros: Simpler signal management, lower wiring costs
Cons: Higher working voltage, more prone to interference for higher frequencies
Currently, signal-ended signals, which are still being used by interface like that of PCI Buses, ISA Buses, LPC buses, etc, referenced the clock as its timing, making it a key factor in influencing the stability of the signal’s transmission/ reception.
During an experience sharing session on a customized motherboard of a European client, AAEON discovered that when the single end waveforms (33 MHz and 14.318 MHz) on an AMD FT1 platform are measured, their rise edge rate and fall edge rate will not match what is specified in the specification. See the tables below. 

For the purpose upholding the internal design quality of AAEON, and improving the boar’s stability, it is highlighted in the systems of ESS experts: Functional testing may be normal, but the board should still attain the quality standards of SI signals when measured. Following the technical documents provided by AMD, it should be noted that a 50pF load capacitor is required for both the rising and falling slew rate, as highlighted in red in the table below.

A 47 pF capacitor is subsequently added at the single clock end.
Please note that measuring from different positions may lead to varying results. The results of re-measured SI signals (with the point the measurement is taken and the measured data) are as shown:

The reference waveform for SI verification
The measured waveform from the PCH

The measured waveform from the PC104 connector

Note: As the length of the layout is different from the component connected at the single clock end, it is through varying the capacitance of the load capacitor needed based on the actual situation that we can deliver a product with both quality and stability to our customers.